(1) Field of the Invention
This invention relates generally to analog-to-digital converters (ADCs), and more particularly to asynchronous successive approximation (ASA) ADCs.
(2) Description of the Prior Art
The analog-to-digital conversion (ADC) is absolutely a prerequisite for digital signal processing. Most signals are analog by nature and have to be converted to digital format for a further digital signal processing. ADC bottlenecks are dynamic range, conversion speed, and power consumption.
Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are frequently the architecture of choice for medium-to-high-resolution applications, typically with sample rates fewer than 5 megasamples per second (Msps). SAR ADCs most commonly range in resolution from 8 to 16 bits and provide low power consumption as well as a small form factor. This combination makes them commonly used for a wide variety of applications, such as portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition.
There is still a need for high performance, low-power and low electromagnetic interference (EMI) ADCs. There are various patents available to improve the performance of ADCs:
U.S. Patent (U.S. Pat. No. 6,747,589 to Srinivasan et al.) teaches a SAR ADC, which is operated by sampling an input voltage and redistributing a corresponding charge among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes performing a bit testing/conversion operation on a last bit of the first group at a second speed which is lower than the first speed to determine the bits of the first group at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of bits of the first group to at least the second level of accuracy.
U.S. Patent (U.S. Pat. No. 6,731,232 to Kearney) discloses a programmable input voltage range analog-to-digital converter in which a split gate oxide process allows the use of high voltage (.+−0.15 volt) switches on the same silicon substrate as standard sub-micron 5-volt CMOS devices. With this process, the analog input voltage can be sampled directly onto one or more sampling capacitors without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitors, the analog input can be scaled or attenuated to suit the dynamic range of the SAR (successive approximation register) ADC itself. In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in the SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range. Once the analog input signal has been attenuated to match the allowed dynamic range of the SAR converter, traditional SAR techniques can be used to convert the input signal to a digital word.
U.S. Patent (U.S. Pat. No. 6,707,403 to Hurrell) discloses an ADC of balanced architecture for determining a digital word corresponding to a sampled voltage of an input signal from an input line comprising a first capacitor circuit comprising a most significant capacitor array and a least significant capacitor array, which are capacitively coupled by a coupling capacitor. A second capacitor circuit coupled to ground balances the first capacitor circuit. A differential comparator compares the voltage on the first capacitor circuit with that on the second capacitor circuit. A SAR responsive to the output of the differential comparator outputs switch bits to a main switch network for selectively switching the capacitors of the first capacitor circuit to respective high and low voltage reference lines until the voltage on first and second inputs and of the differential comparator are equal for determining the digital word corresponding to the sampled voltage on the input line. A first calibration circuit for calibrating the coupling capacitor for compensating for under or over capacitance of the coupling capacitor comprises a plurality of binary weighted first calibrating capacitors, which are coupled by a calibration coupling capacitor to the least significant capacitor array. A first calibration switch network is provided for selectively coupling the first calibrating capacitors to either the second input of the differential comparator, the first input of the differential comparator, or ground. By coupling appropriate ones of the first calibrating capacitors to the second input of the differential comparator over capacitance of the coupling capacitor is compensated for, and under capacitance is compensated for by coupling appropriate ones of the first calibrating capacitors to the first input of the differential comparator.